nips nips2008 nips2008-209 knowledge-graph by maker-knowledge-mining
Source: pdf
Author: Peng Xu, Timothy K. Horiuchi, Pamela A. Abshire
Abstract: We report a compact realization of short-term depression (STD) in a VLSI stochastic synapse. The behavior of the circuit is based on a subtractive single release model of STD. Experimental results agree well with simulation and exhibit expected STD behavior: the transmitted spike train has negative autocorrelation and lower power spectral density at low frequencies which can remove redundancy in the input spike train, and the mean transmission probability is inversely proportional to the input spike rate which has been suggested as an automatic gain control mechanism in neural systems. The dynamic stochastic synapse could potentially be a powerful addition to existing deterministic VLSI spiking neural systems. 1
Reference: text
sentIndex sentText sentNum sentScore
1 edu Abstract We report a compact realization of short-term depression (STD) in a VLSI stochastic synapse. [sent-3, score-0.298]
2 The behavior of the circuit is based on a subtractive single release model of STD. [sent-4, score-0.342]
3 The dynamic stochastic synapse could potentially be a powerful addition to existing deterministic VLSI spiking neural systems. [sent-6, score-0.495]
4 Synaptic transmission is a stochastic process by nature, i. [sent-8, score-0.329]
5 it has been observed that at central synapses transmission proceeds in an all-or-none fashion with a certain probability. [sent-10, score-0.3]
6 The synaptic weight has been modeled as R = npq [1], where n is the number of quantal release sites, p is the probability of release per site, and q is some measure of the postsynaptic effect. [sent-11, score-0.523]
7 The synapse undergoes constant changes in order to learn from and adapt to the ever-changing outside world. [sent-12, score-0.304]
8 The variety of synaptic plasticities differ in the triggering condition, time span, and involvement of preand postsynaptic activity. [sent-13, score-0.22]
9 Regulation of the vesicle release probability has been considered as the underlying mechanism for various synaptic plasticities [1–3]. [sent-14, score-0.4]
10 The stochastic nature of the neural computation has been investigated and the benefits of stochastic computation such as energy efficiency, communication efficiency, and computational efficiency have been shown [4–6]. [sent-15, score-0.316]
11 VLSI stochastic synapse could provide a useful hardware tool to investigate stochastic nature of the synapse and also function as the basic computing unit for VLSI implementation of stochastic neural computation. [sent-17, score-1.115]
12 Although adaptive deterministic VLSI synapses have been extensively studied and developed for neurally inspired VLSI learning systems [8–13], stochastic synapses have been difficult to implement in VLSI because it is hard to properly harness the probabilistic behavior, normally provided by noise. [sent-18, score-0.416]
13 Although stochastic behavior in integrated circuits has been investigated in the context of random number generators (RNGs) [14], these circuits either are too complicated to use for a stochastic synapse or suffer from poor randomness. [sent-19, score-0.786]
14 Stochastic transmission was implemented in software using a lookup table and a pseudo random number generator [15]. [sent-21, score-0.211]
15 Stochastic transition between potentiation and depression has been demonstrated in bistable synapses driven by stochastic spiking behavior at the network level for stochastic learning [16]. [sent-22, score-0.617]
16 Experimental results demonstrated true randomness as well as the adjustable transmission probability. [sent-24, score-0.233]
17 The implementation with ∼ 15 transistors is compact for these added features, although there are much more compact deterministic synapses with as few as five transistors. [sent-25, score-0.263]
18 We also proposed the method to implement plasticity and demonstrated the implementation of STD by modulating the probability of spike transmission. [sent-26, score-0.501]
19 In this paper we extend the subtractive single release model of STD to the VLSI stochastic synapse. [sent-28, score-0.339]
20 We describe a novel compact VLSI implementation of a stochastic synapse with STD and demonstrate extensive experimental results showing the agreement with both simulation and theory over a range of conditions and biases. [sent-30, score-0.574]
21 2 VLSI Stochastic Synapse and Plasticity Vicm Vicm Vdd2 Ibias Vr Vr Vc Vi+ Vg+ M1 M2 Vg- Vw M3 M5 Vp C M4 Vtran Vbias M7 Vo+ M6 Vdd Vpre Vh Vi- Vpre~ Vo- Vdd Vw Vo+ Vo- Figure 1: Schematic of the stochastic synapse with STD. [sent-31, score-0.462]
22 Previously we demonstrated a compact stochastic synapse circuit exhibiting true randomness and consuming very little power (10-44 µW). [sent-32, score-0.778]
23 When a presynaptic spike arrives, Vpre∼ goes low, and transistor M5 shuts off. [sent-37, score-0.409]
24 Vtran either goes high (with probability p) or stays low (with probability 1 − p) during an input spike, emulating stochastic transmission. [sent-42, score-0.284]
25 Fabrication mismatch in an uncompensated stochastic synapse circuit would likely permanently bias the circuit to one solution. [sent-43, score-0.784]
26 By controlling the common-mode voltage of the floating gates, we operate the circuit such that hot-electron injection occurs only on the side where the output voltage is close to ground. [sent-45, score-0.489]
27 Over multiple clock cycles hot-electron injection works in negative feedback to equalize the floating gate voltages, bringing the circuit into stochastic operation. [sent-46, score-0.501]
28 The procedure can be halted to achieve a specific probability or allowed to reach equilibrium (50% transmission probability). [sent-47, score-0.235]
29 The transmission probability can be adjusted by changing the input offset or the floating gate charges. [sent-48, score-0.428]
30 5 1 + erf v−µ , where µ is the input offset voltage for p = 50%, 2δ δ is the standard deviation characterizing the spread of the probability tuning, and v = Vi− − Vi+ is the input offset voltage. [sent-51, score-0.402]
31 Short-term depression is triggered by the transmitted input spikes Vtran to emulate the probability decrease because of vesicle depletion. [sent-54, score-0.421]
32 Short-term facilitation is triggered by the input spikes Vpre to emulate the probability increase because of presynaptic Ca2+ accumulation. [sent-55, score-0.292]
33 3 Short-Term Depression: Model and Simulation Although long-term plasticity has attracted much attention because of its apparent association with learning and memory, the functional role of short-term plasticity has only recently begun to be understood. [sent-58, score-0.18]
34 Recent evidence suggests that short-term synaptic plasticity is involved in many functions such as gain control [17], phase shift [18], coincidence detection, and network reconfiguration [19]. [sent-59, score-0.277]
35 It has also been shown that depressing stochastic synapses can increase information transmission efficiency by filtering out redundancy in presynaptic spike trains [5]. [sent-60, score-1.039]
36 Activity dependent short-term changes in synaptic efficacy at the macroscopic level are determined by activity dependent changes in vesicle release probability at the microscopic level. [sent-61, score-0.367]
37 Since there is a finite pool of vesicles, and released vesicles cannot be replenished immediately, a successful release triggered by one spike potentially reduces the probability of release triggered by the next spike. [sent-64, score-0.745]
38 We propose an STD model based on our VLSI stochastic synapse that closely emulates the simple subtractive single release model [5, 20]. [sent-65, score-0.643]
39 A presynaptic spike that is transmitted reduces the input offset voltage v at the VLSI stochastic synapse by ∆v, so that the transmission probability p(t) is reduced. [sent-66, score-1.332]
40 5 pmax 1 (6) pss ≈ ≈ ∝ 1 + a∆vτd r a∆vτd r r Therefore the steady state mean probability is inversely proportional to the input spike rate when a∆vτd r 1. [sent-74, score-0.543]
41 2(a) and 2(b) show that the mean probability is a linear function of the inverse of the input spike rate at various ∆v and τd for high input spike rates. [sent-83, score-0.807]
42 4 shows that the output spike train exhibits negative autocorrelation at small time intervals and lower power spectral density (PSD) at low frequencies. [sent-88, score-0.756]
43 Figure 2: Mean probability as a function of input spike rate from simulation. [sent-118, score-0.436]
44 Figure 4: Characterization of the output spike train from the simulation of the stochastic synapse with STD. [sent-137, score-0.892]
45 4 VLSI Implementation of Short-Term Depression We implemented this model using the stochastic synapse circuit described above (see Fig. [sent-139, score-0.623]
46 To change the transmission probability we only need to modulate one side of the input, in this case Vi− . [sent-142, score-0.204]
47 The resistor and capacitor provide for exponential recovery of the voltage to its equilibrium value. [sent-143, score-0.2]
48 The input Vi− is modulated by transistors M6 and M7 based on the result of the previous spike transmission. [sent-144, score-0.404]
49 Every time a spike is transmitted successfully, a pulse with height Vh and width Tp is generated at Vp . [sent-145, score-0.592]
50 This pulse discharges the capacitor with a small current determined by Vw and reduces Vi− by a small amount, thus decreasing the transmission probability. [sent-147, score-0.386]
51 The value of the tunable resistors is controlled by the gate voltage of the pFETs, Vr . [sent-148, score-0.272]
52 The update mechanism would then be driven by the presynaptic spike rather than the successfully transmitted spike. [sent-154, score-0.447]
53 The extra components on the left provide for future implementation of short-term facilitation and also symmetrize the stochastic synapse, improving its randomness. [sent-155, score-0.224]
54 The layout size of the stochastic synapse is 151. [sent-158, score-0.493]
55 As a proof of concept, the layout of the circuit is quite conservative. [sent-163, score-0.192]
56 The circuit uses a nominal power supply of 5 V for normal operation. [sent-165, score-0.282]
57 The differential pair comparator uses a separate power supply for hot-electron injection. [sent-166, score-0.219]
58 Each floating-gate pFET has a tunnelling structure, which is a source-drain connected pFET with its gate connected to the floating node. [sent-167, score-0.207]
59 A separate power supply provides the tunnelling voltage to the shorted source and drain (tunnelling node). [sent-168, score-0.323]
60 When the tunnelling voltage is high enough (∼14-15 V), electron tunnels through the silicon dioxide, from the floating gate to the tunnelling node. [sent-169, score-0.479]
61 Alternatively Ultra-Violet (UV) activated conductances may be used to remove electrons from the gate to avoid the need for special power supplies. [sent-171, score-0.216]
62 We raise the power supply of the differential pair comparator to 5. [sent-174, score-0.219]
63 We use the negative feedback operation of hot-electron injection described above to automatically program the circuit into its stochastic regime. [sent-176, score-0.377]
64 During this procedure, STD is disabled, so that the probability at this operating point is the synaptic transmission probability without any dynamics. [sent-178, score-0.384]
65 We use a signal generator to generate pulse signals which serve as input spikes. [sent-180, score-0.265]
66 Although spike trains are better modeled by Poisson arrivals, the averaging behavior should be similar for deterministic spike trains which make testing easier. [sent-181, score-0.754]
67 The power consumption of the STD block is much smaller than the stochastic synapse. [sent-183, score-0.217]
68 We collect output spikes from the depressing stochastic synapse at an input spike rate of 100 Hz. [sent-185, score-1.051]
69 We divide time into bins according to the input spike rate so that in each bin there is either 1 or 0 output spike. [sent-186, score-0.435]
70 In this way, we convert the output spike train into a bit sequence s(k). [sent-187, score-0.385]
71 5 shows the autocorrelation of the output spike trains at two different Vr . [sent-192, score-0.659]
72 6 shows the PSD of the output spike trains from the same data shown in Fig. [sent-195, score-0.409]
73 The time constant of STD increases with Vr so that the larger Vr is, the longer the period of the negative autocorrelation is and the lower the frequencies where power is reduced. [sent-198, score-0.309]
74 Notice that the autocorrelation and PSD for Vr = 1. [sent-200, score-0.25]
75 Normally redundant information is represented by positive autocorrelation in the time domain, which is characterized by power at low frequencies. [sent-203, score-0.309]
76 By reducing the low frequency component of the spike train, redundant information is suppressed and overall information transmission efficiency is improved. [sent-204, score-0.482]
77 If the negative autocorrelation of the synaptic dynamics matches the positive autocorrelation in the input spike train, the redundancy is cancelled and the output is uncorrelated [5]. [sent-205, score-1.089]
78 02 0 50 10 20 30 Intervals 40 50 Figure 5: Autocorrelation of output spike trains from the VLSI stochastic synapse with STD for an input spike rate of 100 Hz. [sent-221, score-1.274]
79 Autocorrelation at zero time represents the sequence variance, and negative autocorrelation at short time intervals indicates STD. [sent-222, score-0.312]
80 59 V r r 0 PSD (dB) 20 0 PSD (dB) 20 −20 −40 −60 −80 0 −20 −40 −60 10 20 30 40 Frequency (Hz) 50 −80 0 10 20 30 40 Frequency (Hz) 50 Figure 6: Power spectral density of output spike trains from the VLSI stochastic synapse with STD for an input spike rate of 100 Hz. [sent-225, score-1.274]
81 We collect output spikes in response to 104 input spikes at input spike rates from 100 Hz to 1000 Hz with 100 Hz intervals. [sent-227, score-0.571]
82 7(a) shows that the mean transmission probability is inversely proportional to the input spike rate for various pulse widths when the rate is high enough. [sent-229, score-0.844]
83 By scaling the probability with the input spike rate, the synapse tends to normalize the DC component of input frequency and preserve the neuron dynamic range, thus avoiding saturation due to fast firing presynaptic neurons and retaining sensitivity to less frequently firing neurons [17]. [sent-231, score-0.833]
84 The slope of mean probability decreases as the pulse width increases. [sent-232, score-0.297]
85 Since the pulse width determines the discharging time of the capacitor at Vi− , the larger the pulse width, the larger the ∆v is and the smaller the slope is. [sent-233, score-0.529]
86 The discharging current is approximately constant, thus ∆v is proportional to the pulse width. [sent-236, score-0.215]
87 01 20 30 40 50 Pulse width (µs) 1/r (a) Mean probability as a function of input spike rate for pulse width Tp =10, 20, 30, 40, 50 µs. [sent-255, score-0.691]
88 Figure 7: Steady state behavior of VLSI stochastic synapse with STD for different pulse widths. [sent-262, score-0.627]
89 As Vr increases, the slope of mean transmission probability as a linear function of 1 decreases. [sent-264, score-0.258]
90 8(a) shows that a∆vτd is approximately an exponential function of Vr , indicating that the equivalent R of the pFET is approximately exponential to its gate voltage Vr . [sent-267, score-0.243]
91 For Vw , the slope of mean transmission probability decreases as Vw increases. [sent-268, score-0.258]
92 8(b) shows that a∆vτd is approximately an exponential function of Vw , indicating that the discharging current from the transistor M6 is approximately exponential to its gate voltage Vw . [sent-271, score-0.326]
93 6 Conclusion We designed and tested a VLSI stochastic synapse with short-term depression. [sent-305, score-0.462]
94 The behavior of the depressing synapse agrees with theoretical predictions and simulation. [sent-306, score-0.404]
95 It is a good candidate to bring randomness and rich dynamics into VLSI spiking neural systems, such as for rate-independent coincidence detection of Poisson spike trains. [sent-309, score-0.446]
96 However, the application of such dynamic stochastic synapses in large networks still remains a challenge. [sent-310, score-0.287]
97 Tsodyks, “An algorithm for modifying neurotransmitter release probability based on pre- and postsynaptic spike timing,” Neural Computation, vol. [sent-327, score-0.55]
98 Zador, “Dynamic stochastic synapses as computational units,” Neural Comput. [sent-333, score-0.287]
99 Abbott, “Redundancy reduction and sustained firing with stochastic depressing synapses,” J. [sent-343, score-0.258]
100 Douglas, “A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity,” IEEE Trans. [sent-414, score-0.195]
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