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Author: David Hsu, Miguel Figueroa, Chris Diorio
Abstract: Competitive learning is a technique for training classification and clustering networks. We have designed and fabricated an 11transistor primitive, that we term an automaximizing bump circuit, that implements competitive learning dynamics. The circuit performs a similarity computation, affords nonvolatile storage, and implements simultaneous local adaptation and computation. We show that our primitive is suitable for implementing competitive learning in VLSI, and demonstrate its effectiveness in a standard clustering task.
Reference: text
sentIndex sentText sentNum sentScore
1 A silicon primitive for competitive learning David Usu Miguel Figueroa Chris Diorio Computer Science and Engineering The University of Washington 114 Sieg Hall, Box 352350 Seattle, W A 98195-2350 USA hsud, miguel, diorio@cs. [sent-1, score-0.358]
2 We have designed and fabricated an 11transistor primitive, that we term an automaximizing bump circuit, that implements competitive learning dynamics. [sent-4, score-0.859]
3 The circuit performs a similarity computation, affords nonvolatile storage, and implements simultaneous local adaptation and computation. [sent-5, score-0.73]
4 We show that our primitive is suitable for implementing competitive learning in VLSI, and demonstrate its effectiveness in a standard clustering task. [sent-6, score-0.352]
5 Upon presentation of a new input to the network, the neuron representing the closest cluster adapts its weight vector, decreasing the difference between the weight vector and present input. [sent-9, score-0.255]
6 Details on this adaptation vary for different competitive learning rules, but the general functionality of the synapse is preserved across various competitive learning networks. [sent-10, score-0.846]
7 These functions are weight storage, similarity computation, and competitive learning dynamics. [sent-11, score-0.371]
8 Many VLSI implementations of competitive learning have been reported in the literature [2]. [sent-12, score-0.257]
9 Digital storage is expensive in terms of die area and power consumption; capacitive storage typically requires a refresh scheme to prevent weight decay. [sent-14, score-0.211]
10 These devices use the floating-gate technology to provide nonvolatile analog storage and local adaptation in silicon. [sent-18, score-0.409]
11 The adaptation mechanisms do not perturb the operation of the device, thus enabling simultaneous adaptation and computation. [sent-19, score-0.435]
12 Unfortunately, the adaptation mechanisms provide dynamics that are difficult to translate into existing neural-network learning rules. [sent-20, score-0.269]
13 [5] proposed a silicon competitive learning synapse that used floating gate technology in the early 90's. [sent-23, score-0.855]
14 However, that approach suffers from asymmetric adaptation due to separate mechanisms for increasing and decreasing weight values. [sent-24, score-0.317]
15 In addition, they neither characterized the adaptation dynamics of their device, nor demonstrated competitive learning with their device. [sent-25, score-0.43]
16 We present a new silicon primitive, the automaximizing bump circuit, that uses synapse transistors to implement competitive learning in silicon. [sent-26, score-1.172]
17 This ll-transistor circuit computes a similarity measure, provides nonvolatile storage, implements local adaptation, and performs simultaneous adaptation and computation. [sent-27, score-0.75]
18 In addition, the circuit naturally exhibits competitive learning dynamics. [sent-28, score-0.629]
19 In this paper, we derive the properties of the automaximizing bump circuit directly from the physics of synapse transistors, and corroborate our analysis with data measured from a chip fabricated in a 0. [sent-29, score-1.08]
20 In addition, experiments on a competitive learning circuit, and software simulations of the learning rule, show that this device provides a suitable primitive for competitive learning. [sent-31, score-0.626]
21 2 Synapse transistors The automaxmizing bump circuit's behavior depends on the storage and adaptation properties of synapse transistors . [sent-32, score-1.101]
22 A synapse transistor comprises a floating-gate MOSFET, with a control gate capacitively coupled to the floating gate, and an associated tunneling implant. [sent-34, score-1.023]
23 The transistor uses floating-gate charge to implement a nonvolatile analog memory, and outputs a source current that varies with both the stored value and the control-gate voltage. [sent-35, score-0.55]
24 The synapse uses two adaptation mechanisms: Fowler-Nordheim tunneling [6] increases the stored charge; impact-ionized hot-electron injection (IHEI) [7] decreases the charge. [sent-36, score-0.828]
25 Because tunneling and IHEI can both be active during normal transistor operation, the synapse enables simultaneous adaptation and computation. [sent-37, score-0.833]
26 A voltage difference between the floating gate and the tunneling implant causes electrons to tunnel from the floating gate, through gate oxide, to the tunneling implant. [sent-38, score-1.636]
27 We can approximate this current (with respect to fixed tunneling and floatinggate voltages, V tunO and V go ) as [4]: (1) where I tunO and Vx are constants that depend on V tunO and V gO , and Ll V tun and Ll Vg are deviations of the tunneling and floating gate voltages from these fixed levels . [sent-39, score-1.252]
28 IHEI adds electrons to the floating gate, decreasing its stored charge. [sent-40, score-0.384]
29 3 Automaximizing bump circuit The automaximizing bump circuit (Fig. [sent-42, score-1.663]
30 1) is an adaptive version of the classic bump-antibump circuit [8]. [sent-43, score-0.368]
31 It uses synapse transistors to implement the three essential functions of a competitive learning synapse: storage of a weight value f1" computation of a similarity measure between the input and f1" and the ability to move f1, closer to the input. [sent-44, score-0.78]
32 MI-M5 form the classic bumpantibump circuit; we added M6-MII and the floating gates. [sent-47, score-0.26]
33 (b) Data showing that the circuit computes a similarity between the input, V in , and the stored value, /-l, for three different stored weights. [sent-48, score-0.604]
34 We augment the bump-anti bump circuit by adding floating gates and tunneling junctions to MI-M5, turning them into synapse transistors; MI and M3 share the same floating gate and tunneling junction, as do M2 and M4. [sent-53, score-2.282]
35 For convenience, we will refer to our new circuit merely as a bump circuit. [sent-55, score-0.778]
36 The charge stored on the bump circuit's floating gates, QI and Q2, shift Imi/S peak away from ~V=O by an amount determined by their difference. [sent-56, score-0.874]
37 We interpret this difference as the weight, p, stored by the circuit, and interpret Imid as a similarity measure between the circuit's input and stored weight. [sent-57, score-0.269]
38 The circuit is automaximizing because tunneling and IHEI naturally tune the peak of Imid to coincide with the present input. [sent-59, score-0.836]
39 This high-level behavior coincides with the dynamics of competitive learning; both act to decrease the difference between a stored weight and the applied input. [sent-60, score-0.404]
40 Therefore, no explicit computation of the direction or magnitude of weight updates is necessary-the circuit naturally performs these computations for us. [sent-61, score-0.455]
41 Consequently, we only need to indicate when the circuit should adapt, not how it does adapt. [sent-62, score-0.347]
42 1 Weight storage The bump circuit's weight value derives directly from the charge on its floatinggates. [sent-66, score-0.657]
43 A synapse transistor's floating-gate charge looks, for all practical purposes, like a voltage source, V" applied to the control gate. [sent-67, score-0.362]
44 This voltage source has a value Vs = QIC i", where Cin is the control-gate to floating-gate coupling capacitance and Q is the floating gate charge. [sent-68, score-0.551]
45 We define the bump circuit's weight, /1, as: (4) This weight corresponds to the value of Yin that equalizes the two floating-gate voltages (and maximizes froid). [sent-70, score-0.649]
46 1 shows the bump circuit's froid output for three weight values, as a function of the differential input. [sent-72, score-0.57]
47 Because floating gate charge is nonvolatile, the weight is also nonvolatile. [sent-74, score-0.549]
48 The differential encoding of the input makes the bump circuit's adaptation symmetric with respect to (Vin -/1). [sent-75, score-0.662]
49 Because the floating gate voltages are independent of the sign of (Vin-/1), the bump circuit's learning rule is symmetric with respect to (Vin-/1). [sent-79, score-1.118]
50 2 Adaptation We now explore the bump circuit's adaptation dynamics. [sent-81, score-0.604]
51 In our subsequent derivations, we consider only positive L1 Vfg , because adaptation is symmetric (albeit with a change of sign). [sent-85, score-0.22]
52 Tunneling causes adaptation by decreasing the difference between the floating-gate voltages V fgl and Vfg2 . [sent-87, score-0.386]
53 Electron tunneling increases the voltage of both floating gates, but, because tunneling increases exponentially with smaller floating-gate voltages (see Eq. [sent-88, score-1.218]
54 Assuming that Ml 's floating gate voltage is lower than M2's, the change in L1 Vfg due to electron tunneling is: d L1 Vfg 1dt = -(I tunl - f tun2 ) 1Cfg (8) We substitute Eq. [sent-90, score-0.905]
55 8 and solve for the tunneling learning rule: d L1Vfg Idt = -ftOe (. [sent-92, score-0.376]
56 ) (9) where ftO=ftunO/Cfp Vx is a model constant, L1 Vo = (L1 Vfgl + L1 V fg2 )12, and f/J models the tunneling mismatch between synapse transistors. [sent-99, score-0.494]
57 (a) Measured adaptation rates, due to tunneling and IHEI, along with fits from Eqs. [sent-124, score-0.508]
58 (b) Composite adaptation rate, along with a fit from (12). [sent-126, score-0.173]
59 We slowed the IHEI adaptation rate (by using a higher Vinj ), compared with the data from part (a), to cause better matching between tunneling and IHEI. [sent-127, score-0.55]
60 ~ V rg ; and the The circuit also uses IHEI to decrease ~ Vrg . [sent-130, score-0.409]
61 We bias the bump circuit so that only transistors Ml and M2 exhibit IHEI. [sent-131, score-0.91]
62 Consequently, we decrease ~ V rg by controlling the drain voltages at Ml and M2. [sent-134, score-0.276]
63 Coupled current mirrors (M6-M7 and M8-M9) at the drains of Ml and M2, simultaneously raise the drain voltage of the transistor that is sourcing a larger current, and lower the drain voltage of the transistor that is sourcing a smaller current. [sent-135, score-0.704]
64 The transistor with the smaller source current will experience a larger V sd , and thus exponentially more IHEI, causing its source current to rapidly increase. [sent-136, score-0.272]
65 Diodes (MlO and M11) further increase the drain voltage of the transistor with the larger current, further reducing its IHEI. [sent-137, score-0.306]
66 The net effect is that IHEI acts to equalize the currents, and, likewise, the floating gate voltages . [sent-138, score-0.572]
67 Recently Hasler proposed a similar method for controlling IHEI in a floating gate differential pair [4]. [sent-139, score-0.448]
68 Assuming II >h, the change in ~ V rg due to IHEI is: (10) We expand the learning rule by substituting Eq. [sent-140, score-0.166]
69 To compute values for the drain voltages of MI and M 2 , we assume that all of II flows through MIl and all of 12 flows through M7. [sent-143, score-0.259]
70 Like tunneling, the IHEI rule depends on three factors: a controllable learning rate, Vinj ; the difference between Yin and f. [sent-145, score-0.161]
71 2 shows measurements of d~ Vrgldt versus ~ Vfg due to tunneling and IHEI, along with fits to Eqs. [sent-148, score-0.335]
72 IHEI and tunneling facilitate adaptation by adding and removing charge from the floating gates, respectively. [sent-150, score-0.836]
73 Isolated, any of these mechanisms will eventually drive the bump circuit out of its operating range. [sent-151, score-0.833]
74 There is an added benefit to combining tunneling and IHEI: Part (a) Fig 2 shows that tunneling acts more strongly for smaller values of ~ Vfg , while IHEI shows the opposite behavior. [sent-153, score-0.69]
75 The mechanisms complement each other, providing adaptation over more than a I V range in ~ Vrg . [sent-154, score-0.228]
76 11 to derive the bump learning rule: --d~Vrg / dt =/tOe (~Vtun - ~I'o)/V, . [sent-157, score-0.494]
77 When ~ V fg is small, adaptation is primarily driven by IHEI, while tunneling dominates for larger values of ~ Vfg • The bump learning rule is unlike any learning rule that we have found in the literature. [sent-160, score-1.153]
78 First, it naturally moves the bump circuit's weight towards the present input. [sent-162, score-0.519]
79 Second, the weight update is symmetric with respect to the difference between the stored value and the present input. [sent-163, score-0.216]
80 Third, we can vary the weight-update rate over many orders of magnitude by adjusting Vlun and V inj • Finally, because the bump circuit uses synapse transistors to perform adaptation, the circuit can adapt during normal operation. [sent-164, score-1.516]
81 4 Competitive learning with bump circuits We summarize the results of simulations of the bump learning rule and also results from a competitive learning circuit fabricated in the TSMC 0. [sent-165, score-1.73]
82 We first compared the performance of a software neural network on a standard clustering task, using the bump learning rule (fitted to data from Fig. [sent-169, score-0.623]
83 2), and a basic competitive learning rule (learning rate p=O. [sent-170, score-0.342]
84 On an input presentation, the network updated the weight vector of the closest neuron using either the bump learning rule, or Eq. [sent-174, score-0.635]
85 3 shows that the bump circuit's rule performs favorably with the hard competitive learning rule. [sent-179, score-0.774]
86 3) comprised two neurons with a one-dimensional input (a neuron was a single bump circuit), and a feedback network to control adaptation. [sent-181, score-0.55]
87 The feedback network comprised a winner-take-all (WT A) [10] that detected which bump was closest to the present input, and additional circuitry [9] that generated Vtun and Vinj from the WT A output. [sent-182, score-0.586]
88 We tested this circuit on a clustering task, to learn the centers of a mixture of two Gaussians. [sent-183, score-0.383]
89 3, we compare the performance of our circuit with a simulated neural network using Eq. [sent-185, score-0.376]
90 The VLSI circuit performed comparably with the neural network, demonstrating that our bump circuit, in conjunction with simple feedback mechanisms, can implement competitive learning in VLSI. [sent-187, score-1.087]
91 We can generalize the circuitry to multiple dimensions (multiple bump circuits per neuron) and multiple neurons; each neuron only requires one V lun and V inj signal. [sent-188, score-0.604]
92 3 X10' + Hard competitive learning rule o bump learning rule 2. [sent-189, score-0.861]
93 (a) Comparison of a neural network using the bump learning rule versus a standard competitive learning rule. [sent-194, score-0.824]
94 (c) Performance of a competitive learning circuit versus a neural network for learning a mixture of two Gaussians. [sent-197, score-0.674]
95 Q) circuit output I + + ~+ 05 :J > target values - + ~ 06 04 neural network output + o =:-: . [sent-200, score-0.376]
96 Schneider, "Analog VLSI circuits for competitive learning networks", in Analog Integrated Circuits and Signal Processing, 15, pp. [sent-228, score-0.337]
97 Diorio, "A p-channel MOS synapse transistor with self-convergent memory writes", IEEE Transactions on Electron Devices, vol. [sent-231, score-0.291]
98 Snow, "Fowler- Nordheim tunneling into thermally grown Si0 2", Journal of Applied Physics, vol. [sent-245, score-0.335]
99 Delbruck, "Bump circuits for computing similarity and dissimilarity of analog voltages", CNS Memo 26, California Institute of Technology, 1993. [sent-253, score-0.198]
100 Diorio, "A silicon primitive for competitive learning," UW CSE Technical Report no . [sent-257, score-0.317]
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