nips nips2001 nips2001-34 nips2001-34-reference knowledge-graph by maker-knowledge-mining
Source: pdf
Author: Toshihiko Yamasaki, Tadashi Shibata
Abstract: A flexible pattern-matching analog classifier is presented in conjunction with a robust image representation algorithm called Principal Axes Projection (PAP). In the circuit, the functional form of matching is configurable in terms of the peak position, the peak height and the sharpness of the similarity evaluation. The test chip was fabricated in a 0.6-µm CMOS technology and successfully applied to hand-written pattern recognition and medical radiograph analysis using PAP as a feature extraction pre-processing step for robust image coding. The separation and classification of overlapping patterns is also experimentally demonstrated. 1 I ntr o du c ti o n Pattern classification using template matching techniques is a powerful tool in implementing human-like intelligent systems. However, the processing is computationally very expensive, consuming a lot of CPU time when implemented as software running on general-purpose computers. Therefore, software approaches are not practical for real-time applications. For systems working in mobile environment, in particular, they are not realistic because the memory and computational resources are severely limited. The development of analog VLSI chips having a fully parallel template matching architecture [1,2] would be a promising solution in such applications because they offer an opportunity of low-power operation as well as very compact implementation. In order to build a real human-like intelligent system, however, not only the pattern representation algorithm but also the matching hardware itself needs to be made flexible and robust in carrying out the pattern matching task. First of all, two-dimensional patterns need to be represented by feature vectors having substantially reduced dimensions, while at the same time preserving the human perception of similarity among patterns in the vector space mapping. For this purpose, an image representation algorithm called Principal Axes Projection (PAP) has been de- veloped [3] and its robust nature in pattern recognition has been demonstrated in the applications to medical radiograph analysis [3] and hand-written digits recognition [4]. However, the demonstration so far was only carried out by computer simulation. Regarding the matching hardware, high-flexibility analog template matching circuits have been developed for PAP vector representation. The circuits are flexible in a sense that the matching criteria (the weight to elements, the strictness in matching) are configurable. In Ref. [5], the fundamental characteristics of the building block circuits were presented, and their application to simple hand-written digits was presented in Ref. [6]. The purpose of this paper is to demonstrate the robust nature of the hardware matching system by experiments. The classification of simple hand-written patterns and the cephalometric landmark identification in gray-scale medical radiographs have been carried out and successful results are presented. In addition, multiple overlapping patterns can be separated without utilizing a priori knowledge, which is one of the most difficult problems at present in artificial intelligence. 2 I ma g e re pr es e n tati on by P AP PAP is a feature extraction technique using the edge information. The input image (64x64 pixels) is first subjected to pixel-by-pixel spatial filtering operations to detect edges in four directions: horizontal (HR); vertical (VR); +45 degrees (+45); and –45 degrees (-45). Each detected edge is represented by a binary flag and four edge maps are generated. The two-dimensional bit array in an edge map is reduced to a one-dimensional array of numerals by projection. The horizontal edge flags are accumulated in the horizontal direction and projected onto vertical axis. The vertical, +45-degree and –45-degree edge flags are similarly projected onto horizontal, -45-degree and +45-degree axes, respectively. Therefore the method is called “Principal Axes Projection (PAP)” [3,4]. Then each projection data set is series connected in the order of HR, +45, VR, -45 to form a feature vector. Neighboring four elements are averaged and merged to one element and a 64-dimensional vector is finally obtained. This vector representation very well preserves the human perception of similarity in the vector space. In the experiments below, we have further reduced the feature vector to 16 dimensions by merging each set of four neighboring elements into one, without any significant degradation in performance. C i r cui t c o nf i g ura ti ons A B C VGG A B C VGG IOUT IOUT 1 1 2 2 4 4 1 VIN 13 VIN RST RST £ ¡ ¤¢ £ ¥ §¦ 3 Figure 1: Schematic of vector element matching circuit: (a) pyramid (gain reduction) type; (b) plateau (feedback) type. The capacitor area ratio is indicated in the figure. The basic functional form of the similarity evaluation is generated by the shortcut current flowing in a CMOS inverter as in Refs. [7,8,9]. However, their circuits were utilized to form radial basis functions and only the peak position was programmable. In our circuits, not only the peak position but also the peak height and the sharpness of the peak response shape are made configurable to realize flexible matching operations [5]. Two types of the element matching circuit are shown in Fig. 1. They evaluate the similarity between two vector elements. The result of the evaluation is given as an output current (IOUT ) from the pMOS current mirror. The peak position is temporarily memorized by auto-zeroing of the CMOS inverter. The common-gate transistor with VGG stabilizes the voltage supply to the inverter. By controlling the gate bias VGG, the peak height can be changed. This corresponds to multiplying a weight factor to the element. The sharpness of the functional form is taken as the strictness of the similarity evaluation. In the pyramid type circuit (Fig. 1(a)), the sharpness is controlled by the gain reduction in the input. In the plateau type (Fig. 1(b)), the output voltage of the inverter is fed back to input nodes and the sharpness changes in accordance with the amount of the feedback. ¥£¡ ¦¤¢ £¨ 9&% ¦©§ (!! #$ 5 !' #$ &% 9 9 4 92 !¦ A1@9 ¨¥ 5 4 52 (! 5 8765 9) 0 1 ¥ 1 ¨
[1] G.T. Tuttle, S. Fallahi, and A.A. Abidi. (1993) An 8b CMOS Vector A/D Converter. in ISSCC Tech. Digest, vol. 36, pp. 38-39. IEEE Press.
[2] G. Cauwenberghs and V. Pedroni. (1995) A Charge-Based CMOS Parallel Analog Vector Quantizer. In G. Tesauro, D. S. Touretzky and T.K. Leen (eds.), Advances in Neural Information Processing Systems 7, pp. 779-786. Cambridge, MA: MIT Press.
[3] M. Yagi, M. Adachi, and T. Shibata. (2000) A Hardware-Friendly Soft-Computing Algorithm for Image Recognition. X European Signal Processing Conf., Sept. 4-8, 2000 (EUSIPCO 2000), Vol. 2, pp. 729-732, Tampere, Finland.
[4] M. Adachi and T. Shibata. (2001) Image Representation Algorithm Featuring Human Perception of Similarity for Hardware Recognition Systems. In Proc. of the Int. Conf. on Artificial Intelligence (IC-AI'2001), Ed. by H. R. Arabnia, Vol. I, 229-234 (CSREA Press, ISDBN: 1-892512-78-5), Las Vegas, Nevada, USA, June 25-28, 2001.
[5] T. Yamasaki and T. Shibata. (2001) An Analog Similarity Evaluation Circuit Featuring Variable Functional Forms. In Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2001), Vol. 3, pp. III-561-564, Sydney, Australia, May. 7-9, 2001.
[6] T. Yamasaki, K. Yamamoto and T. Shibata. (2001) Analog Pattern Classifier with Flexible Matching Circuitry Based on Principal-Axis-Projection Vector Representation. In Proc. 27th European Solid-State Circ. Conf. (ESSCIRC 2001), Ed. by F. Dielacher and H. Grunbacher, pp. 212-215 (Frontier Group), Villach, Austria, September 18-20, 2001.
[7] J. Anderson, J. C. Platt, and D. B. Kirk. (1993) An Analog VLSI Chip for Radial Basis Functions. In S. J. Hanson, J. D. Cowan, and C. L. Giles Eds., Advances in Neural Information Processing Systems 5, pp. 765-772., San Maetro, CA; Morgan Kaufmann.
[8] L. Theogarajan and L. A. Akers. (1996) A Multi-Dimentional Analog Gaussian Radial Basis Circuit. In Proc. IEEE Int. Symp. Circuits Syst. (ISCAS ’96), Vol. 3, pp. III-543 -546 Atlanta, GA, USA, May, 1996.
[9] L. Theogarajan and L. A. Akers. (1997) A scalable low voltage analog Gaussian radial basis circuit. IEEE Trans. on Circuits and Systems II, Volume 44, No. 11, pp. 977 –979, 1997.
[10] K. Ito, M. Ogawa and T. Shibata. (2001) A High-Performance Time-Domain Winner-Take-All Circuit Employing OR-Tree Architecture. In Proc. 2001 Int. Conf. on Solid State Devices and Materials (SSDM2001), pp. 94-95, Tokyo, Japan, Sep. 26-28, 2001.